[Coursera] VLSI CAD: Logic to Layout by Rob A. Rutenbar (University of Illinois at Urbana-Champaign)
Coursera

coursera-vlsi-cad-logic-to-layout (218 files)
Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.txt 2.64kB
Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.srt 4.05kB
Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.mp4 5.25MB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.txt 5.20kB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.srt 7.94kB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.mp4 10.09MB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.txt 4.17kB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.srt 6.34kB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.mp4 7.32MB
Lectures/01_Orientation/01_Course_Promo_Video.mp4 2.71MB
Assignements/Final Exam/0_Final_Exam.png 1.44MB
Lectures/04_BDDs_SAT_Week_2/02_Lecture_3.2-_BDD_Basics_Part_2_16-51.srt 22.33kB
Lectures/04_BDDs_SAT_Week_2/04_Lecture_3.4-_BDD_Ordering_28-12.txt 25.48kB
Lectures/04_BDDs_SAT_Week_2/07_Lecture_4.3-_Sat_For_Logic_25-45.mp4 30.12MB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.txt 16.61kB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.srt 25.35kB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.mp4 23.39MB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.txt 14.05kB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.srt 21.15kB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.mp4 19.36MB
Lectures/04_BDDs_SAT_Week_2/04_Lecture_3.4-_BDD_Ordering_28-12.srt 38.60kB
Lectures/04_BDDs_SAT_Week_2/07_Lecture_4.3-_Sat_For_Logic_25-45.txt 23.34kB
Lectures/04_BDDs_SAT_Week_2/04_Lecture_3.4-_BDD_Ordering_28-12.mp4 34.82MB
Lectures/04_BDDs_SAT_Week_2/01_Lecture_3.1-_BDD_Basics_Part_1_15-17.mp4 19.13MB
Lectures/04_BDDs_SAT_Week_2/01_Lecture_3.1-_BDD_Basics_Part_1_15-17.srt 22.04kB
Lectures/04_BDDs_SAT_Week_2/01_Lecture_3.1-_BDD_Basics_Part_1_15-17.txt 14.45kB
Lectures/04_BDDs_SAT_Week_2/02_Lecture_3.2-_BDD_Basics_Part_2_16-51.mp4 20.85MB
Lectures/04_BDDs_SAT_Week_2/03_Lecture_3.3-_BDD_Sharing_17-00.txt 13.81kB
Lectures/04_BDDs_SAT_Week_2/02_Lecture_3.2-_BDD_Basics_Part_2_16-51.txt 14.46kB
Lectures/04_BDDs_SAT_Week_2/07_Lecture_4.3-_Sat_For_Logic_25-45.srt 36.35kB
Lectures/04_BDDs_SAT_Week_2/03_Lecture_3.3-_BDD_Sharing_17-00.mp4 21.19MB
Lectures/04_BDDs_SAT_Week_2/03_Lecture_3.3-_BDD_Sharing_17-00.srt 21.33kB
Lectures/09_ASIC_Routing_Week_7/07_11.7_Implementation_Mechanics-_Data_Structures__Constraints__18-02.mp4 27.72MB
Lectures/09_ASIC_Routing_Week_7/09_11.9_From_Detailed_Routing_to_Global_Routing_15-48.srt 22.66kB
Lectures/09_ASIC_Routing_Week_7/09_11.9_From_Detailed_Routing_to_Global_Routing_15-48.mp4 27.42MB
Lectures/09_ASIC_Routing_Week_7/08_11.8_Implementation_Mechanics-_Depth-First_Search_14-06.txt 14.05kB
Lectures/09_ASIC_Routing_Week_7/08_11.8_Implementation_Mechanics-_Depth-First_Search_14-06.srt 21.47kB
Lectures/09_ASIC_Routing_Week_7/08_11.8_Implementation_Mechanics-_Depth-First_Search_14-06.mp4 24.84MB
Lectures/09_ASIC_Routing_Week_7/07_11.7_Implementation_Mechanics-_Data_Structures__Constraints__18-02.txt 17.85kB
Lectures/09_ASIC_Routing_Week_7/07_11.7_Implementation_Mechanics-_Data_Structures__Constraints__18-02.srt 27.43kB
Lectures/09_ASIC_Routing_Week_7/06_11.6_Implementation_Mechanics-_How_Expansion_Works_23-31.txt 24.99kB
Lectures/09_ASIC_Routing_Week_7/03_11.3_Maze_Routing-_Multi-Point_Nets_12-24.txt 12.47kB
Lectures/09_ASIC_Routing_Week_7/06_11.6_Implementation_Mechanics-_How_Expansion_Works_23-31.srt 38.50kB
Lectures/09_ASIC_Routing_Week_7/06_11.6_Implementation_Mechanics-_How_Expansion_Works_23-31.mp4 28.74MB
Lectures/09_ASIC_Routing_Week_7/05_11.5_Maze_Routing-_Non-Uniform_Grid_Costs_14-57.txt 14.98kB
Lectures/09_ASIC_Routing_Week_7/05_11.5_Maze_Routing-_Non-Uniform_Grid_Costs_14-57.srt 22.78kB
Lectures/09_ASIC_Routing_Week_7/05_11.5_Maze_Routing-_Non-Uniform_Grid_Costs_14-57.mp4 21.52MB
Lectures/09_ASIC_Routing_Week_7/04_11.4_Maze_Routing-_Multi-Layer_Routing_12-21.txt 12.55kB
Lectures/09_ASIC_Routing_Week_7/04_11.4_Maze_Routing-_Multi-Layer_Routing_12-21.srt 19.19kB
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Bibtex:
@article{,
title= {[Coursera] VLSI CAD: Logic to Layout by Rob A. Rutenbar (University of Illinois at Urbana-Champaign)},
keywords= {},
journal= {},
author= {Coursera},
year= {},
url= {},
license= {},
abstract= {},
superseded= {},
terms= {}
}


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