| Info hash | 625ae5f99f1cfdc2b8eb42577ca5271ad78967e0 |
| Last mirror activity | 5:57 ago |
| Size | 1.44GB (1,436,500,392 bytes) |
| Added | 2016-07-14 01:32:05 |
| Views | 2614 |
| Hits | 4804 |
| ID | 3238 |
| Type | multi |
| Downloaded | 6309 time(s) |
| Uploaded by |
 courses
|
| Folder | coursera-vlsi-cad-logic-to-layout |
| Num files | 218 files [See full list] |
| Mirrors | 14 complete, 0 downloading = 14 mirror(s) total [Log in to see full list] |
[Coursera] VLSI CAD: Logic to Layout by Rob A. Rutenbar (University of Illinois at Urbana-Champaign)
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10 day statistics (2 downloads)
| Average Time | 2 hrs, 05 mins, 42 secs |
| Average Speed | 190.47kB/s |
| Best Time | 1 hrs, 25 mins, 50 secs |
| Best Speed | 278.93kB/s |
| Worst Time | 2 hrs, 45 mins, 34 secs |
| Worst Speed | 144.60kB/s |